The present invention relates to the field of semiconductor devices, and, more particularly, to semiconductor power devices. The invention is well suited for discrete power devices, as well as power devices co-integrated on the same chip with drive and control circuits, for example.
In general, in a monolithic semiconductor power device, such as one implemented with VIPower technology, for example, a voltage divider or an equivalent element for monitoring the substrate voltage will be integrated in the sector with the low voltage control circuitry. According to one prior art approach, this function is implemented using an integrated resistor divider between the substrate and the control region. An alternative prior art approach is that the detection element is an integrated capacitor through which variations in the substrate voltage are sensed.
In such devices the substrate typically coincides with the collector terminal/drain terminal/electrode of the power transistor that in many cases (e.g., VIPower, power integrated circuit (PIC), etc.) is connected to the external circuit through a bottom or back metal layer of the substrate. Relatively high voltages may be applied to the substrate (e.g., up to 2000 V), and thus any integrated resistor divider or integrated capacitor used for sensing the substrate voltage will need to withstand such voltages.
If a capacitor is used for sensing voltage variations, the capacitor is commonly implemented via a p/n junction. Yet, this approach has drawbacks such as, for example, that the capacitance value varies significantly with the applied voltage. In particular, for relatively high (i.e.,  greater than 100 V) voltages the capacitance tends to decrease to very small values, thus making detection of voltage variations thereon very difficult.
This problem, which is typical of integrated junction capacitors, may be addressed by using a dielectric-type capacitor. Of course, the thickness and electrical characteristics of the dielectric material should be adequate to withstand the intense electric field that may be present between the capacitor plates, and at the highest rated voltage. Silicon oxide, deposited or grown according to common semiconductor device fabrication techniques, is an excellent dielectric that may be used even with a relatively large thickness (around 1-2 xcexcm) without significant fabrication difficulties.
Nevertheless, using a relatively thick dielectric significantly limits the capacitance that may be obtained per unit area according to the known physical law (C=xcex50xc2x7xcex5rxc2x7A/d) where d is the thickness of the dielectric and A is the area of the capacitor. Thus, to have capacitors of sufficiently large capacitance for sensing of substrate voltage variations, even at very low frequencies a relatively large integration area is required. Yet, this represents a significant burden. As such, designers tend to favor less area consuming alternatives to dielectric-type summing capacitors.
An object of the present invention is to provide for the integration of a high voltage dielectric-type capacitor for sensing the substrate voltage in monolithic power devices without undue silicon area consumption.
Generally speaking, the present invention provides this and other features by utilizing the edge or perimeter structure common to many monolithic semiconductor power devices for implementing a capacitor for sensing substrate voltage. More particularly, as is well known to those skilled in the art, in many semiconductor power devices (whether integrated or discrete) there is typically a perimeter or edge diffusion region. This perimeter region is generally ten or more micrometers wide, and more particularly about 20-50 xcexcm wide, and it surrounds the area where the power device is integrated.
The perimeter region is also spaced a uniform distance from the integration area, typically several tens of xcexcm, and more particularly about 50 to 150 xcexcm therefrom. Moreover, the perimeter region is usually heavily doped with a dopant of the same type of conductivity of the substrate and electrically connected thereto. The purpose of the perimeter region is to make the electric field around the device as uniform as possible, thus the heavy doping to make it highly conducting.
A continuous metal layer is often deposited and defined directly in contact with the doped silicon of the edge region. This is done to make the edge region even more conductive for a collector or drain that surrounds the area occupied by the power device, and also potentially for the drive and control circuitry of the power device. In practice, since the edge region is so highly conductive and in electric contact with the semiconductor substrate, it may be considered an extension of the collector electrode that is commonly represented by the metallization layer of the back or bottom of the semiconductor chip.
It has been found that a capacitor for sensing the substrate voltage may be efficiently and economically implemented by isolating a portion or segment of the metal layer that normally covers this heavily doped edge region of electric field equalization. Moreover, an isolation dielectric layer of silicon oxide is not removed from the surface of this semiconductor substrate, as is normally done on the remaining portion of the perimeter region, before depositing the metal. This remaining layer of isolated silicon oxide becomes the dielectric layer of the capacitor.
The plates of the capacitor are the heavily doped perimeter region that is electrically connected to the substrate (i.e., drain or collector region), and the segment of metal that is isolated from the remaining metal layer and defined directly over the heavily doped edge region. Through successive process steps a conducting path may be defined from the second plate to a relative voltage sensing node of the circuit for monitoring the substrate voltage.
In addition to having a relatively negligible integration area requirement, such a substrate voltage sensing capacitor is a dielectric-type capacitor. As such, it is not subject to capacitance changes due to variations of the applied voltage. Moreover, the relatively large thickness of the layer of isolation oxide (commonly above 1 xcexcm) that is normally deposited over the perimeter region is quite capable of withstanding the rated voltage (i.e., up to or even above 2000 V).